1. Field of the Invention
The present invention relates to a method for modeling a device and a network to be analyzed to perform a complex simulation for analyzing in a complex manner a semiconductor device and a network that includes the device.
2. Description of the Related Art
There have been known a complex simulation to analyze in a complex manner the devices included in a network together with the network. This complex simulation combines a device simulation technique for analyzing the characteristics of a semiconductor device, such as a metal oxide semiconductor (MOS) transistor, on a device-by-device basis, and a circuit simulation technique for analyzing the characteristics of the entire network. This type of simulation techniques has been disclosed in patent literature, for example, Japanese Unexamined Patent Application Publication No. 09-082938 or Japanese Unexamined Patent Application Publication No. 2000-260973.
In a typical complex simulation, a device model formed by modeling the device to be analyzed two-dimensionally or three-dimensionally and a network model showing the remaining network portion are integrated, then the device model is analyzed by device simulation. Subsequently, the parameters obtained from the device analysis and the net list of the network prepared in advance are used to analyze the entire network by a circuit simulation. This makes it possible to know the characteristics of the device operated in the network. A source code for a complex simulation is usually created by modifying a general-purpose source code for device analyses and the modified general-purpose source code is integrated with a circuit analysis source code through the intermediary of an interface code.
When attention is focused on a plurality of devices of a network in a complex simulation, according to the prior arts, each device model is handled as a separate analysis region, and the device analysis is carried out on each region. For instance, in a two-dimensional complex simulation focused on a complementary MOS (CMOS) transistor using a pair of n-type and p-type MOS transistors (hereinafter referred to simply as “CMOS”), the n-type and the p-type MOS transistors are separately subjected to the device analysis.
However, when a plurality of devices is handled, it will be required to consider a plurality of device analysis regions when creating a source code. This inconveniently complicates the adjustment of the interface between the devices and circuit analyses, taking much time to create the source code.